The present invention relates to semiconductor devices including carbon nanotubes, such as a vertical nanotube transistor/capacitor cell.
There are continuing goals in semiconductor fabrication to reduce the number of masks or steps needed to fabricate semiconductor devices, e.g., memory cell devices such as DRAMs. Likewise, there is a continuing goal to shrink the size of such devices thereby maximizing the density of the resulting chip or die. Lastly, there is a desire to provide such devices that perform consistently.
There has been some recent interest in the use of carbon nanotubes due to their remarkable properties. Researchers have found carbon nanotubes to be stronger and tougher than steel, capable of carrying higher currents than either copper or superconductors, and able to form transistors a few nanometers across. In addition, nanotubes have high thermal conductivity and are stable at high temperatures. E. Lerner, Putting Nanotubes to Work, The Industrial Physicist, 22-25 (December 1999). Further, carbon nanotubes may have a consistent resistance (predicted to be about 6.0 kilohms) regardless of the length of the tube due to the intrinsic characteristics of ballistic transport in such nanotubes. A. Kasumov, Supercurrents Through Single-Walled Carbon Nanotubes, Science, 284, 1508-1510 (May 1999). Currently, the resistance of conventional semiconductor devices varies due to the doping means that are used to produce the desired resistance. Thus, the consistent resistance of a nanotube would be of particular value for semiconductor devices. However, neither the form that particular nanotube semiconductor devices would take nor methods for mass production of nanotube semiconductor devices are currently known or available.
The present invention provides vertical nanotube semiconductor devices and methods for making the same. An embodiment of the semiconductor devices of the present invention comprises a vertical transistor/capacitor cell including a nanotube (a hollow tube). The device includes a vertical transistor and a capacitor cell both using a single nanotube to form the individual devices.
The present invention also provides a semiconductor device comprising vias for electrical interconnections between layers of integrated circuits. Specifically, an embodiment of a via according to the present invention may comprise a first trace layer, a nanotube (e.g., a carbon tube) having a lower end connected to the first trace layer, the nanotube being substantially orthogonal to the first trace layer. A second trace layer is electrically connected to an upper end of the nanotube. Thus, the nanotube forms a via or electrical interconnection between the first and second trace layers.
The present invention also provides a semiconductor device comprising a logic stack or multi-gate stack device including a stack of transistors formed about a vertical nanotube. The multi-gate stack may include two transistors in series, such as for an AND gate. The small size and predictable resistivity of the nanotubes used in this device provide unique advantages.
The present invention further provides methods for forming semiconductor devices having multiple vertical nanotubes using patterned nucleation materials formed upon semiconductor substrates.
All of the specifically described methods and semiconductor devices are set forth for illustration of the methods and devices of the present invention. It is understood, however, that the present invention is not limited to those specifically described embodiments of the methods and devices.